This course covers the analysis of CMOS digital integrated circuits at the transistor level. Topics include MOS transistor operation. CMOS inverter analysis, including Noise Margins Levels, delay using RC and Elmore models, logical effort, power dissipation, CMOS logic families circuits. It also focuses on the Introduction to layout design and stick diagram. The course also introduces the wiring engineering model in the interconnect RC Model, parasitic extraction, coupling capacitance, and delay impact in deep submicron. Students perform simulation, verification, and layout using EDA tools, completing a team-based implementation of introductory assignments and projects.