Abstract:  

FINFET transistors' leakage current resources at nanoscale technology will be investigated, analyzed and discussed in this paper; such as, Subthreshold leakage current, tunneling leakage current, and source-drain leakage current. The main SPICE parameters which influence the leakage current will be also discussed. Different techniques and models were used to reduce the leakage current will be compared, an efficient technique used for sub-nano transistors are also invstigated to reduce leakage current at minimum value, FINFET DoubleGate Transistor is shown that it is the promising technique to operate at 5nm gate channel. Results based on BSIMCMG107, and NEMO5 simulation tools at Birck Center at Purdue University are tested and used. Comparing between these techniques, FINFET transistors seems to be the most efficient low power technique comparing with other efficient one.