Abstract:  

Leakage power is the dominant source of power dissipation for Sub-100 nm VLSI (very large scale integration) circuits. Various techniques were proposed to reduce the leakage power at nano-scale; one of these techniques is MTV (multi-threshold voltage). In this paper, the exact and optimal value of threshold voltage (Vth) for each transistor in any sequential circuit in the design is found, so that the value of the total leakage current in the design is at the minimum.