Decimal arithmetic has received considerable attention
recently due to its suitability for many financial and
commercial applications. In particular, numerous algorithms
have been recently proposed for decimal multiplication. A major
approach to decimal multiplication shaped by these proposals is
based on performing the decimal digit-by-digit multiplication in
binary, converting the binary partial product back to decimal,
and then adding the decimal partial products as appropriate
to form the final product in decimal. With this approach, the
efficiency of binary-to-BCD partial product conversion is critical
for the efficiency of the overall multiplication process. A recently
proposed algorithm for this conversion is based on splitting the
binary partial product into two parts (i.e., two groups of bits),
and then computing the contributions of the two parts to the
partial BCD result in parallel. This paper proposes two new
algorithms (Three-Four split and Four-Three split) based on this
principle . We present our proposed architectures that implement
these algorithms and compare them to existing algorithms. The
synthesis results show that the Three-Four split algorithm runs
15%faster and occupies 26.1%less area than the best performing
equivalent circuit found in the literature. Furthermore, the Four-
Three split algorithm occupies 37.5% less area than the state of
the art equivalent circuit.